JUNG HWAN KIM

System Engineering Department
University of Arkansas at
Little Rock

Little Rock, AR 72204-1099
TEL: 501-569-3296 / FAX: 501-569-8698
email: jhkim@ualr.edu

 

 

RESEARCH INTERESTS

 

Bioinformatics (Prediction of transcriptional regulatory elements in Dictyostelium), Genetic Algorithm, VLSI Design.

 

SUMMARY OF CURRENT RESEARCH

 

The goal of my current bioinformatics research is to predict transcriptional regulatory elements (TREs) associated with classes of developmentally regulated genes in Dictyostelium discoideum (Dd), through the application of pattern recognition algorithm techniques, with larger amount of collected data and utilizing a statistically significant scoring method. Dd is a facile system for basic biomedical research in cell and developmental biology, having unique advantages for studying fundamental cellular processes with powerful molecular genetic tools, processes either absent or less accessible in other organisms. For this reason, the NIH has chosen Dd as a model organism for functional analysis of sequenced genes. I and my students have been developing the pattern recognition algorithm that can predict TREs. The developed algorithm will be based on the dynamic programming (DP) matching technique. DNA sequences of Dd can be classified into 4 classes based on the result of the timing of gene expression during development. We will compare upstream DNA sequences from these 4 different classes with candidate TREs and find common and unique characteristic TREs controlling gene expressions in each Dd developmental class. We will determine a class-specific expression of genes from the Dd cDNA projects a the University of Tsukuba in Japan. The upstream DNA sequence for these genes will then be accessed from a Dd genomic DNA database at San Diego Supercomputer Center. To measure the validity of a candidate TRE, we will evaluate E-score based on the similarity score using the DP matching technique. We will also develop the criteria to select TREs from the candidate TREs with statistical significance.

 

EDUCATION

 

Ph.D., University of Iowa, 1987, Electrical and Computer Eng.

Thesis : On the Design of Easily Testable and Reconfigurable Systolic Arrays
Thesis Adviser : Sudhakar M. Reddy

 

M.S., University of Iowa, 1982, Electrical and Computer Eng.

B.S., Seoul National University, Seoul, Korea, 1979, Electrical Eng.

 

 

PROFESSIONAL EXPERIENCE

 

  • Tenured Full Professor (July 2000 - present), Systems Engineering, University of Arkansas at Little Rock.
  • Tenured Associate Professor of Computer Engineering (May 1994 – May 2000), The Center for Advanced Computer Studies, University of Louisiana.
  • Komatsu Chair Visiting Associate Professor (Sep. 1994 - Aug. 1995), Graduate School of Information Science, Japan Advanced Institute of Science and Technology, Japan.
  • Assistant Professor of Computer Engineering (Jan. 1988 - April 1994), The Center for Advanced Computer Studies, University of SW Louisiana.
  • Research Assistant (Aug. 1983 - Dec. 1987), Department of Electrical and Computer Eng. University of Iowa. Participated in Semiconductor Research Cooperation (SRC) project.
  • Teaching Assistant (Aug. 1981 - July 1983), Department of Electrical and Computer Eng. University of Iowa.
  • Engineer (May 1979 - May 1981), Department of Biomedical Engineering, Seoul National University Hospital. Developed software for the image analysis of Computer-Aided Tomography.

 

PUBLICATIONS

 

Books

 

1.        Kim, J. H. and T. R. N. Rao (Edited), "1994 International Synposium on Defect and Fault-Tolerance in VLSI Systems", IEEE Press, Oct. 1994.

2.        (Book Chapter) Kim, J. H. and S. K. Park, "Learning and Application of Binary Neural Networks", in Neural network Systems Techniques and Applications (edited by C. T. Leondes), Academy Press, 2000.

 

Patent

 

1.        Kim, J. H. and S. K. Park, "The Geometrical Learning of Binary Neural Networks", U.S. patent number:5,980,079, date of patent: Nov. 9, 1999

2.        Kim, J. H. and H. S. Oh, "The Design of a Non-coherent PN Code Acquisition Chip Using Dual Matched Filters", submitted the patent application form

 

Journals

 

1.        Kim, J. H. and S. M. Reddy, "On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement," Special Issue on High-Yield VLSI Systems of IEEE Transactions on Computers, Vol. 38, No. 4, PP.515-525, April, 1989.

2.        Kim, J. H. and P. K. Rhee, "A Resource-Efficient Reconfiguration Algorithm for VLSI 2-D Processor Arrays", Journal of VLSI Signal Processing, Kluwer Academic, Vol. 4, PP.317-330, 1992.

3.        Kim, J. H. and S. M. Reddy, "On Easily Testable and Reconfigurable Two-Dimensional Systolic Arrays," Computer System Science and Engineering, CRL publishing, Vol. 3, No.3, PP.212-219, July, 1992.

4.        Kim, J. H., P. K. Rhee and D. S. Ha, "Optimal Domain-Based Reconfiguration Algorithm for WSI Processor Arrays", Microprocessing and Microprogramming - The Euromicro Journal, North-Holland, Vol. 33, PP. 261-278, 1992.

5.        Park, S. K. and J. H. Kim, "A Geometrical Learning Algorithm for Multilayer Neural Networks in a Binary Field", IEEE Transactions on Computers, Vol. 42, No. 8, pp.988-992, Aug. 1993.

6.        Kim, J. H. and P. K. Rhee, "The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays", IEEE Transactions on Computers, Vol. 42, No. 11, pp.1403-1408, Nov. 1993.

7.        Kim, J. H. and K. Efe, "A Parallel Reconfiguration for WSI/VLSI Processor Arrays", Microprocessors and Microsystems, Butterworth, vol. 17, No. 6, PP. 353-360, 1993.

8.        D.D. Wei, J.H. Kim and T.R.N. Rao, "Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays", Journal of Microelectronic Systems Integration, Kluwer Academic, Vol. 1 (3), PP.221-233, Dec. 1993

9.        Szu, H., J. H. Kim, and I. Kim, "Live Neural Network Formations on Electronic Chips", Neurocomputing 6, pp.551-564, Oct. 1994.

10.   Lo, J.L. and J.H. Kim, "Highly Available Memory Systems with Fault Tolerant Associative Repair Mechanisms", Journal of Microelectronic Systems Integration, Kluwer Academic, Vol. 3, No.1, pp.205-215, 1995

11.   Kim, J. H. and S. K. Park, "The Geometrical Learning of Binary Neural Networks", IEEE Trans. on Neural Networks, Vol. 6, No. 1, PP.237-247, Jan. 1995.

12.   Rhee, P. K., J. H. Kim, and M. A. Bayoumi, "Channel Complexity Analysis and Optimal Reconfiguration Algorithm for WSI Processor Arrays", accepted at Intl. Journal of VLSI Computer-Aided Design.

13.   Liu, T., F. Lombardi, S. Horiguchi, and J.H. Kim, "A Structured Walking-1 Approach for the Diagnosis of Interconnect and FPICs", Trans. on Information and Systems, Institute of Electronics, Informations, Communications Engineers of Japan, Vol. E79-D, No. 1, Jan. 1996

14.   Sarin, S. J., H. Delic and J. H. Kim, "Slotted-Ring Local Area Networks with Multiple Priority Stations", Telecommunication Review, Vol 8, No. 4, pp.653-662, Sept. 1998.

15.   Yasunaga, M., I. Hachiya, and J. H. Kim, " Fault-Tolerant Self-Organizing Map Implemented by Wafer Scale Integration", IEEE Trans. on VLSI Systems, Vol.6, No. 2, pp.257-265, June 1998.

16.   Kim J. H., S. Sarin, M. Yasunaga, and H. Oh, "Robust Non-Coherent PN Code Acquisition for CDMA Communication Systems", IEEE Trans. on Vehicular Technology, Vol.50, No.1, pp.278-286, Jan. 2001.

17.   Choi Y., J. Park, H. Kim, and J. H. Kim, "Optimal Trajectory Planning and Sliding Move Control for Robots Using Evolution Strategy", Robotica. Cambridge University press, Vol. 18, pp.423-428, Sep. 2000.

18.   Yasunaga M., I. Yoshihara, and J. H. Kim,The Evolutionary Algorithm-based Reasoning System”, IEICE Trans. On Information and Systems, Vol.E84-D, No.11, pp.1508-1520, November 2001.

19.   Yasunaga M., T.Nakamura, I. Yoshihara, and J. H. Kim,  “The Kernel-based Pattern Recognition System Designed by Genetic Algorithm”, IEICE Trans. On Information and Systems, Vol.E84-D, No.11, pp.1528-1539, November 2001.

20.   Yasunaga M., I. Yoshihara, and J.H. Kim, " Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation”, Journal of Genetic Programming and Evolvable Machines (Kluwer Academic Publishers), Vol.2, No. 3, pp.211-230, 2001.

21.   Kim, J.H. and M. Yasunaga, "Back-propagation Learning on a Bus-based Neurocomputer with Integer Representation", submitted to Neurocomputing

22.   Yasunaga, M, M. Takahashi, and J.H. Kim, "The Application of Genetic Algorithms to the Design of Reconfigurable Reasoning VLSI Chip's", submitted to IEEE Trans. on Evolutionary Computing

23.   Yasunaga, M. and J.H. Kim, "Data Direct Implementation Approach to the Design of Sonar Recognition VLSI Chip", submitted to IEE Proceeding.

 

 

Conference Proceedings

  

 

68. Seo, D., M. Yasunaga, and J. H. Kim, “A Computational Approach to Detect transcriptional regulatory elements in Discoideum”, 2004 Proc. IEEE Congress on Evolutionary Computing (CEC2004), June. 2004.

67. Seo, D., M. Yasunaga, and J. H. Kim, “A Bioinformatics Approach to Predict transcriptional regulatory elements in Dictyostelium gene expression”, 2004 Institute of Biological Engineering Meeting (2004 IBE), Jan. 2004.

66. Yasunaga M., I. Yoshihara, and J. H. Kim, “Segmental-Transmission-Line for High-Speed Digital Signals and Its Design Using Genetic Algorithms”, 2003 Proc. IEEE Congress on Evolutionary Computing (CEC2003), Dec. 2003.

65. Yasunaga M., K. Ushiyama, I. Yoshihara, and J. H. Kim, “The application of genetic algorithms to the genome sequence analysis”, 2002 International Conference on Artificial Intelligence and Soft Computing (ASC 2002), July 2002.

64. Aibe N., M. Yasunaga, K. Ushiyama, I. Yoshihara, and J. H. Kim, “A probabilistic neural network hardware system using a learning parameter parallel architecture”, 2002 IJCNN.

63. Yasunaga M., K. Ushiyama, Aibe N., I. Yoshihara, and J. H. Kim, “An evolutionary kernal-based reasoning system using reconfigurable VLSIs”,2002 Proc. IEEE Congress on Evolutionary Computing (CEC2002).

62. Kim, S. W, D. S. Ha, J. H. Kim, and J. H. Kim, “Performance of Smart Antennas with Adaptive Combining at Handsets for the 3GPP WCDMA System,” IEEE Vehicular Technology Conference, October 2001.

61. Kim, S. W, D. S. Ha, and J. H. Kim, "Performance Gain of Smart Antennas with Hybrid Combining at Handsets for the 3GPP WCDMA System" Wireless Personal Multimedia Communication 2001, Sep. 2001.

60. Yasunaga M., I. Yoshihara, and J.H. Kim, “The Application of Evolvable Reasoning Hardware to the Genome Informatics”, Proc. Artificial Intelligence and applications, Sep. 2001, Spain.

59. Yasunaga M., J.H. Kim and I. Yoshihara, " Evolvable Reasoning Hardware,” Proc. IEEE Congress on Evolutionary Computing (CEC2001), May 2001, Seoul, Korea.

58. Yasunaga M., Taro Nakamura, Ikuo Yoshihara, and Jung H. Kim, "Kernel Optimization in Pattern Recognition Using a Genetic Algorithm," Proc. Genetic and Evolutionary Computation Conf., pp.391, July 2000.

57. Yasunaga, M, J.H. Kim, and M. Takahashi, "The Application of Genetic Algorithms to the Design of Reconfigurable Reasoning VLSI Chip's", accepted at International Symposium on FPGA, Feb. 2000.

56. Kim, I., L. Liu, N. Siears, J.H. Kim, and T. Gilbertson, "Regionalized expression of aquaporins suggests a role for water channels in osmotic sensing by taste cells", Society for Neuroscience Abstract 25:871.13, Oct. 1999.

55. Chang, J.W., D.K. Sung, and J.H. Kim, "An adaptive channel resolution scheme for soft-handoff in cellular DS/CDMA systems, Vehicular Technology Conference 1999 (VTC'99), June 1999.

54. Yasunaga, M. and J.H. Kim, "Parallel SOM Using Multiple Stimuli", accepted at Int'l Joint Conf. on Neural Networks 1999

53. Lathia, B. and J. H. Kim, "Variable Rate Decisions in the QCELP Coder Using Competitive Neural Networks for Wireless communications", accepted at Int'l Joint Conf. on Neural Networks 1999

52. Lathia, B. and J. H. Kim, "Using Learning Vector Quantifiers for Network Bandwidth Optimization in the QCELP Speech Code", accepted at Int'l Joint Conf. on Neural Networks 1998 (IJCNN'98), Alaska, May 1998.

51. Kim, J. H., H. S. Oh and S. J. Sarin, "A Robust Code Acquisition Architecture for Non-Coherent Systems using Dual Matched Filters", accepted at Vehicular Technology Conference 1998 (VTC'98), Ottawa Canada, May 1998.

50. Kim, J.H., S.K. Park, Y.N. Han, and H.S. Oh, "Efficient VLSI implementation of a 3-layer threshold network", Proc. of 1997 International Conference on Neural Networks, Houston, TX, June 1997.

49. D.S. Han, S.K. Park, and J.H. Kim, "Application of Artificial Neural Networks to the Synchronization Problem of DS/CDMA Wireless Communication System", Proc. of International Conference on Telecommunications, Istanbul, Turkey, Apr. 1996.

48. Yamamori, K., J. H. Kim, and S. Horiguchi, "The Efficient Design of Fault-Tolerant Artificial Neural Networks", Proc. of 1995 International Conference on Neural Networks, Australia, Dec. 1995.

47. V. Purohit, F. Lombardi, S. Horiguchi, and J.H. Kim, "Diagnosing Multiple Bridge Faults in Baseline Multistage Interconnection Networks", Proc. of 1995 International Conference on Parallel Processing, Illinois, Aug. 1995.

46. J.H. Kim, K. Yamamori, and S. Horiguchi, "The Fault-Tolerant Design of Artificial Neural Networks", Proc. of 1995 Joint Technical Conference on Computers and Communications, Kumamoto, Japan, July 1995.

45. D.S. Han, S.K. Park, and J.H. Kim, "Acquisition System of DS/CDMA Using Binary Neural Network", Proc. of 2nd Asia-Pacific Conference on Communications, Osaka, Japan, June 1995.

44. J.H. Kim and S. Horiguchi, "The Synthesis of Threshold Networks", Proc. of 1995 Pacific Asia Conference on Expert Systems, Huangshan, China, May 1995.

43. J.H. Kim, "Cost-Effective Checksum Tests in Algorithm-Based Fault-Tolerance on 2-D Processor Arrays", 5th Wafer Scale Integration Workshop, Saitama, Japan, March 1995.

42. Y.C. Chang, S. Jorge, and J.H. Kim, "A Module-Sliced High Yield WSI Memory System", Proc. of IEEE Intl. Conf. on Wafer Scale Integration, San Francisco, CA, Jan. 1995.

41. D.D. Wei, G.Y. Song, J.H. Kim and T.R.N. Rao, "Robust Checksum Tests in Algorithm-Based Fault-Tolerance on 2-D Processor Arrays", Proc. of 1994 International Symposium on Parallel Architectures Algorithms and Networks, Kanazawa, Japan, Dec. 1994.

40. D.D. Wei, J.H. Kim and T.R.N. Rao, "Roundoff Error-Free Tests in Algorithm-Based Fault-Tolerance on 2-D Processor Arrays", Proc. of 1994 Intl. Workshop on Defect and Fault Tolerance in VLSI Systems, Montreal, CA., Oct. 1994.

39. J.H. Kim, S.K. Park, and I.S. Kim, "The Convergent Learning of Three-Layer Artificial Neural Networks for Any Binary-to-Binary Mapping", Proc. of 1994 IEEE International Conference on Neural Networks, Orlando, FL, June 1994.

38. C.H. Chu, J.H. Kim, and I.S. Kim, "Applications of binary neural networks learning to pattern classification", Proc. of 1994 IEEE International Conference on Neural Networks, Orlando, FL, June 1994.

37. Q. Zhang and J.H. Kim, "An Efficient Method to Reduce Roundoff Error in Matrix Multiplication with Algorithm-Based fault-Tolerance", Proc. of IEEE Intl. Conf. on Wafer Scale Integration, San Francisco, CA, Jan. 1994

36. C. H. Chu and J. H. Kim, "Pattern Classification by Geometrical Learning of Binary Neural Networks", Proc. of Intl. Joint Conf. on Neural Networks, Nagoya, Japan, Oct. 1993.

35. J.H. Kim and B. Ham, "The Learning of Multi-Output Binary Neural Networks for Handwritten Digit Recognition", Proc. of Intl. Joint Conf. on Neural Networks, Nagoya, Japan, Oct. 1993.

34. D.D. Wei, J.H. Kim and T.R.N. Rao, "Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays", Proc. of IEEE Intl. Workshop on Defect and Fault Tolerance in VLSI Systems, Venice, Italy, Oct. 1993

33. S.-K. Park and J.H. Kim, "Localized Geometrical Training methods of Feedforward Networks for Pattern Classification Problems", Proc. of World Congress on Neural networks, Portland, OR, July 1993.

32. J.H. Kim, B. Ham, C. Lursinsap, and S.-K. Park, "Handwritten Digit Recognition using Binary Neural Networks", Proc. of World Congress on Neural networks, Portland, OR, July 1993.

31. Szu, H., J. H. Kim, and I. Kim, "Self Architecture- Theory and Experiment of Biological Neural Networks", Proc. of 1993 IEEE Intl. Conf. on Neural Networks, San Francisco, CA, March 1993.

30. Kim, J. H., T. R. N. Rao, G. L. Feng, and J. C. Lo, "The Efficient Design of Strongly Fault-Secure ALU Using a Reduced Berger Code for WSI Processor Arrays", to appear at 1993 International Conference on Wafer Scale Integration, San Francisco, CA, Jan. 1993.

29. Szu, H., J. H. Kim, and I. Kim, "Live Neural Network Formations on Electronic Chips", Proc. of Intl. Joint Conf. on Neural Networks 1992, Beijing, China, Nov. 1992.

28. Kim, J. H. and S. K. Park, "The Geometrical Learning of Multi-Layer Artificial Neural Networks with Guaranteed Convergence" Proc. of Intl. Joint Conf. on Neural Networks 1992, Baltimore, ME. PP.871-876, June, 1992.

27. Kim, J. H. and P. K. Rhee, "An On-Line Reconfiguration Algorithm of WSI Processor Arrays", Intl. Symp. on Circuit and System, San Diego, CA, PP.2953-2956, May, 1992.

26. Park, S. K., A. Marston and J. H. Kim, "On the Structural Requirements of Multilayer Perceptrons in a Binary Field", IEEE Southeastern Symposium on System Theory, Greensville, NC, PP.203-207, March 1992.

25. Kim, J. H. and P. K. Rhee, "A Rule-Based Reconfiguration of WSI Processor Arrays", Int'l. Conf. on Wafer Scale Integration, San Francisco, CA, PP.75-84, Jan. 1992.

24. Kim, J. H. and H. Sung, "An Enhanced One-Step C-Testable Design of Two-Dimensional Iterative Logic Arrays", Int'l. Conf. on Wafer Scale Integration, San Francisco, CA, PP.331-340, Jan. 1992.

23. Kim, J. H. and P. K. Rhee, "A Parallel Reconfiguration Algorithm for WSI Processor Arrays", Proc. of Int'l Conference on Parallel Processing, Illinois, PP.670-671, Aug., 1991.

22. Kim, J. H. and S. K. Park, "Synthesis of Three-Layer Perceptrons for Parity Functions," Proc. of Intl. Joint Conf. on Neural Networks 1991, Seattle, WA. PP.992-995, July, 1991.

21. Kim, J. H., C. Lursinsap and S. K. Park, "Fault-Tolerant Artificial Neural Networks," Proc. of Intl. Joint Conf. on Neural Networks 1991, Seattle, WA. PP.951-951, July, 1991.

20. Park, S. K. and J. H. Kim, "Competitive Learning of Three-Layer Perceptrons," Proc. of Intl. Joint Conf. on Neural Networks 1991, Seattle, WA. PP.926-926, July, 1991.

19. Lursinsap, C., H. Chu and J. H. Kim, "Analytical Weight Shifting Models for Self-Recovery Networks," Proc. of Intl. Joint Conf. on Neural Networks 1991, Seattle, WA. PP.951-951, July, 1991.

18. Park, S. K., J. H. Kim and H. S. Chung, "A Training Algorithm for Discrete Multilayer Perceptrons", Proc. of Int'l Symp. on Circuit and System, Singapore, PP.2140-2143, Jun., 1991.

17. Kim, J. H. and P. K. Rhee, "Optimal Domain-Based Reconfiguration Algorithm for WSI Processor Arrays", Proc. of Int'l Symp. on Circuit and System, Singapore, PP.1493-1496, Jun., 1991.

16. Lursinsap, C. and J. H. Kim, "Parallel Learning for Back-Propagation Network in Binary Field", Proc. of Int'l Symp. on Circuit and System, Singapore, PP.1477-1500, Jun. 1991.

15. Park, S. K. and J. H. Kim, "A Linearization Technique for Linearly Inseparable Patterns," Proc. of 23rd Southeastern Symp. on System Theory, Columbia, SC, PP.207-211, March 1991.

14. Rhee, P. K. and J. H. Kim, "A Variable Domain Approach to The Reconfiguration of WSI 2-D Array Processors", Int'l. Conf. on Wafer Scale Integration, San Francisco, CA, PP.134-140, Jan. 1991.

13. Kim, J. H. and Rhee, P. K., "Channel Complexity Analysis for Reconfigurable VLSI/WSI Processor Arrays", International Conference on Application Specific Array Processors, Princeton, NJ, Sep. 1990.

12. Rhee, P. K., J. H. Kim and Youn Y. H., "A Novel Reconfiguration Scheme for 2-D Processor Arrays", Proceedings of 1989 IEEE Intl. Conf. on Computer-Aided Design, San Jose, CA, PP.230-233, November, 1989.

11. Youn, H. Y., A. D. Singh and J. H. Kim, "An Efficient Reconfiguration Scheme for WSI of Cube-Connected Cycles with Bounded Channel Width", Proceedings of 1989 Intl. Workshop on Defect and Fault Tolerance in VLSI Systems, Orlando, FL, October, 1989.

10. Kim, J. H. and P. K. Rhee, "Domain Approach to Reconfiguration Algorithm", 1989 Intl. Workshop on Hardware Fault Tolerance in Multiprocessors, Urbana Champaine, IL, June, 1989.

9. Kim, J. H. and P. K. Rhee, "Reconfiguration Algorithm of Fault-Tolerant Two-Dimensional VLSI Array", Proceedings of 1989 Intl. Symp. on Circuits and Systems, Portland, Oregon, PP.394-399, May, 1989.

8. Kim, J. H. "On the Design of Easily Testable and Reconfigurable Systolic Arrays," Proceedings of the Intl. Conf. on Systolic Arrays, San Diego, CA, PP.505-514, May, 1988.

7. Kim, J. H. and S. M. Reddy, "Fault-tolerant L-U Decomposition in a 2-D Systolic Array," Proceedings of the 1987 Princeton Workshop on Algorithm, Architecture and Technology Issues in Model of Concurrent Computation, Plenum Press, Princeton, NJ, PP.585-596, Oct. 1987.

6. Kim, J. H. and S. M. Reddy, "On the Design of Testable Fault-tolerant VLSI Processor Arrays," Proceedings of the International Workshop on Designing for Yield, University of Oxford Press, London, England, July 1987.

5. Kim, J. H. and S. M. Reddy, "On the Design of Easily Testable and Reconfigurable Two-dimensional VLSI Processor Arrays," Proceedings of the Sixteenth International Conference on Parallel Processing, Pennsylvania State University Press, St. Charles, Il, PP.101-109, July 1987.

4. Kim, J. H., "On-Line Detection of Errors in Homogeneous Multiprocessor Systems," Proceedings of the 1986 Real-Time System Symposium, New Orleans, LA, PP.55-62, December, 1986.

3. Kim, J. H., "Concurrent Error Detection in FFT Networks," Proceedings of the Twenty-fourth Allerton Conference on Communication, Control and Computing, Urbana Champaign, Il, October, 1986.

2. Kim, J. H. and S. M. Reddy, "A Fault-tolerant Systolic Array Design Using TMR Method," Proceedings of the 1985 International Conference on Computer Design, New York, NY, PP.769-773, October, 1985.

1. Jhon, C. S. and J. H. Kim, "Towards Applicative Specification of Concurrent Digital Systems," Proceedings of the 1984 IEEE Workshop on Language for Automation, Princeton, NJ, PP.19-24, November, 1984.

 

 

RESEARCH GRANTS

 

1.        NIH, "Partnership for Biomedical Research in Arkansas", $6,097,462, Sep. 2001 – Oct. 2004 (P.I.: Dr. Larry Cornette).

2.        NSF, "Orosensory Signal Processing and Cell-To-Cell Communication", $495,855 June 1, 1999 - May 31, 2001 (Pending).

3.        Electronics & Telecommunication Research Institute, "Design of the Neural Network based Acquisition System for CDMA Digital Cellular Communications", $92,356 June 1, 1996 - Dec. 31, 1998.

4.        System Engineering Research Institute, "Application of Binary Neural Networks to Speech Recognition", $26,700, Aug. 1996 - July 1997.

5.        NSF, "Fault-Tolerant Neural Networks: Design Theories and Applications", $2,818,000, Jan. 1, 1992- July 31, 1996. (P.D.: Dr. T.R.N. Rao)

6.        Office of Naval Research, "Facility for Live Formation of Biological Neural Networks on a VLSI Chip", $76,545, Sep.1993- Sep. 1996.

7.        Japan Ministry of Education, "International Joint Research Project on Reconfigurable Parallel Processors", $243,000, Apr. 1, 1993 - Mar. 31, 1996 (P.D.:Dr. S. Horiguchi)

8.        Office of Naval Research, "Facilities for Large Scale Neural Networks Study", $85,342, July, 1993- June 1994

9.        Board of Regents, State of Louisiana, LEQSF, "Live Neural Network Formations on a VLSI Chip", $74,055, June 1, 1993 - May 31, 1995

10.   NSF, "Feasibility Study of Biological Neural Network Formations on a VLSI Chip", $35,745, Aug. 1, 1993- Jan. 31, 1995

11.   Board of Regents, State of Louisiana, LEQSF, "The Geometrical Learning of Artificial Neural Networks", $70,300, June 1, 1992-May 31, 1994.

12.   Summer Research Award, University of SW Louisiana, 1991.

13.   Board of Regents, State of Louisiana, LaSER Program, "The Design of Fault-Tolerant Processor Arrays Using Self-Checking Processors", $7,000, May 1, 1991- August 31 1991.

14.   Board of Regents, State of Louisiana, LaSER Program, "Fault-Tolerant Systems and Self-Checking Circuits", $290,000, Jan. 1, 1988- Dec. 31 1992, (P.D.: Dr. T.R.N. Rao)

 

 

STUDENTS SUPERVISED

 

1.  Phill K. Rhee, Ph. D. in Computer Science, "On the Reconfiguration of VLSI/WSI Processor Arrays", Dec. 1990

2.  B. Jhon, Ph.D. in Computer Engineering (Co-advising with Dr. C. Lursinsap), "A new Approach to High Level Synthesis with Statistical Based Micro-Rollback and Self-Recovery", May 1993,

3.  David D. Wei, Ph.D. in Computer Science (Co-advising with Dr. T.R.N. Rao), "Complete Checking in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays", Dec. 1993

4.  B. H. Ham, Ph.D. in Computer Engineering, "Handwritten Digit Recognition Using Binary Neural Networks", Dec. 1993

5.  G. Y. Song, Ph. D. in Computer Engineering, "Robust Checking in Algorithm-Based Fault-Tolerance on 2-D Processor Arrays", Aug. 1995

6.  Max J. Patin and 10 students, M.S. in Computer Engineering.

 

 

PROFESSIONAL ACTIVITY

 

Colloquia and Seminars

l        University of South Florida, April 1998

l        Tokyo Institute of Technology, August, 1997

l        University of Nebraska, May 1996.

l        Electronics & Telecommunication Research Institute (ETRI), Aug. 1995.

l        Pusan National University, Aug. 1995.

l        Kyushu Institute of Technology, July 1995.

l        Yatsushiro National College of Technology, July 1995.

l        Beijing University, May 1995.

l        Yamagata National University, April 1995.

l        Chiba National University, March 1995.

l        Tokyo Institute of Technology, August, 1994

l        Japan Advanced Institute of Science and Technology (JAIST), Feb. 1993

l        Kanazawa National University, Feb. 1993

l        Nippon Telegraph and Telephone (NTT), Feb. 1993

l        Toyo University, Feb. 1993

l        Tennessee Technological Univ., Oct. 1992

l        Gold Star Central Lab., Korea, Aug. 1992

l        Dongkuk Univ., Korea, Dec. 1991

l        Korea Electrical Lab., Korea, Dec. 1991

l        Korea Univ., Korea, July 1989

l        Seoul National Univ., Korea, July 1989

l        Hyundae Electronics Co., Korea, July 1989

l        Hanyang Univ., Korea, July 1989

l        Korea Advanced Inst. of Science and Tech., Korea, July 1989

 

 

Referee

 

IEEE Trans. on Computers

IEEE Trans. on CAD

IEEE Computer

IEEE Trans. on Neural Networks

IEEE Trans. on CAS

 

 

Proposal Reviewer

 

NSF MIPS Program

NSF IT Program

 

 

Professional Involvement

 

l        Program Chairman, 1994 IEEE Intl. Symposium on Defect and Fault-Tolerance in VLSI Systems, Oct. 1994

l        Program Committee, 2001 IEEE Asia-pacific Conference on Dependable computing, Dec. 2001.

l        Session Chairman, 2001 International Conference on Artificial Intelligence on Applications, Sep. 2001

l        Session Chairman, 2000 International Conference on Neural Information processing, Nov. 2000

l        Program Committee, 1999 IEEE Intl. Symposium on Defect and Fault-Tolerance in VLSI Systems, Nov. 1999

l        Session Chair, 1998 IEEE Intl. Joint Conference on Neural Networks, May 1998

l        Program Committee, 1998 IEEE Intl. Symposium on Defect and Fault-Tolerance in VLSI Systems, Nov. 1998

l        Program Committee, 1997 IEEE International Conf.: Innovative System In Silicon, Oct. 1997.

l        Program Committee and Session Chairman, 1997 IEEE Intl. Symposium on Defect and Fault-Tolerance in VLSI Systems, Oct. 1997.

l        Program Committee, The 3rd International Conference on Multi-Dimensional Mobile Communications, July 1997.

l        Program Committee and Session Chairman, 1996 IEEE International Conf.: Innovative System In Silicon, Oct. 1996.

l        Program Committee, The 2nd International Conference on Multi-Dimensional Mobile Communications, July 1996.

l        Session Chairman, 1995 Pacific-Asia Conf. on Expert Systems, May, 1995

l        Program Committee, 1994 Intl. Conference on Neural Information Processing, Nov. 1994

l        Program Committee and Session Chairman, 1994 IEEE Intl. Conf. on Wafer Scale Integration, Jan. 1994.